The Assumptions That Break Designs
There’s a particular kind of design failure that’s frustrating because it’s so preventable. The simulation looked clean. The bench prototype measured well. But somewhere between initial characterization and real-world deployment, performance fell short — and the root cause traced back to a clocking assumption that was never fully validated.
In precision timing and RF systems, those assumptions usually circle back to the frequency synthesizer. Specifically, to the gap between what engineers expect from a synthesizer based on simplified mental models, and what the hardware actually delivers under real operating conditions.
This blog addresses that gap directly. We’re going to walk through the most persistent misconceptions about frequency synthesis performance, explain what’s actually happening at a physical level, and give you a clearer framework for making better decisions on your next design.
Misconception One: Phase Noise Is a Single Number
Ask most engineers to characterize a frequency synthesizer’s phase noise and they’ll cite a single value — typically at a 10 kHz or 100 kHz offset. That number shows up on the data sheet front page and gets used as the primary comparison metric between products.
The problem is that phase noise is a spectral quantity, not a single number. It varies significantly with offset frequency, and different applications care about very different regions of that spectrum.
In wireless communications and ADC clocking, integrated jitter over a specific bandwidth — typically 12 kHz to 20 MHz for many telecom applications — is the specification that connects directly to system performance. In radar, close-in phase noise at offsets of a few hundred hertz to a few kilohertz often dominates clutter performance, because that’s where target returns compete with noise in the slow-moving target regime.
A frequency synthesizer that looks competitive at 100 kHz offset may have substantially worse performance at 1 kHz offset — and that distinction is invisible if you’re only looking at the headline number. Always get the full phase noise plot across the relevant offset range and integrate it over the bandwidth your application actually uses.
Misconception Two: Jitter Only Matters for Digital Systems
This one costs RF designers real performance. The assumption is that jitter is a digital timing concern — something to worry about in SerDes links and ADC clocking — while RF systems care about phase noise, not jitter.
In practice, they’re describing the same thing from different perspectives. And the jitter → phase noise conversion is direct and consequential. For a frequency synthesizer running at 10 GHz, a 100-femtosecond RMS jitter contribution corresponds to roughly -80 dBc/Hz integrated phase noise — which in a receiver architecture translates into a tangible noise floor elevation.
For system architects designing wideband receivers, phased array radars, or high-dynamic-range test instrumentation, the jitter performance of every clock source in the chain — including the frequency synthesizer driving the local oscillator — contributes to the system noise floor in ways that can’t be easily recovered downstream.
This is precisely where Jitter attenuators earn their place in the architecture. When the reference signal arriving at your synthesizer has been degraded by board-level routing, switching regulator noise, or other system contributors, attenuation of that jitter before it enters the synthesis chain prevents those impairments from being multiplied by the synthesizer’s multiplication factor and appearing at the output.
Misconception Three: A Faster Switching Speed Is Always Better
Wideband frequency synthesis applications — radar, frequency-hopped communications, electronic warfare — often emphasize frequency switching speed as a key selection criterion. The assumption is that faster is universally better.
It’s not that simple. Switching speed and phase noise exist in fundamental tension in most PLL-based frequency synthesizer architectures. A wider loop bandwidth enables faster settling but also passes more VCO phase noise to the output. A narrow loop bandwidth filters VCO noise more effectively but extends settling time.
The right choice depends on your application’s specific requirements. A continuous FMCW radar that dwells at a given frequency for microseconds before stepping needs fundamentally different loop bandwidth optimization than a frequency-hopped system that changes frequency every few milliseconds.
Understanding this tradeoff gives you more informed conversations with your frequency synthesis vendor — and helps you evaluate whether a claimed switching speed is actually relevant to your operating mode or just an impressive data sheet number.
Misconception Four: All 28nm CMOS Synthesizers Are Equivalent
Process node has become a marketing talking point in the semiconductor industry. Two different frequency synthesizers built on 28nm CMOS can have dramatically different performance characteristics depending on how the architecture exploits the process.
What 28nm actually enables — when the architecture is designed to take advantage of it — is a level of digital integration that earlier processes couldn’t support. Specifically, it allows embedded DSP algorithms that continuously monitor and compensate for temperature drift, supply voltage variation, and process corners in real time. This adaptive compensation is what enables consistent performance across the full operating range, not just at the nominal condition where the part was characterized.
Mixed-Signal Devices built their entire timing platform around this principle. Their Virtual Crystal™ technology uses the digital density of 28nm CMOS to implement autonomous compensation that keeps oscillator and synthesizer performance stable across the -40°C to 105°C extended temperature range — a meaningful advantage in defense, aerospace, and outdoor infrastructure applications where temperature variation is a real operating condition, not an edge case.
Misconception Five: You Can Fix a Bad Reference with a Good Synthesizer
This is perhaps the most damaging assumption because it leads to designs where the clocking chain is never treated as a system.
A frequency synthesizer cannot improve on the quality of its reference. It can maintain the reference’s phase noise floor, multiply it up in frequency (with the expected 20 log N degradation), and add its own noise contributors on top. What it cannot do is clean up a degraded, jittery reference before synthesizing from it. That’s not what the synthesis architecture is doing.
This is why the full clocking chain deserves attention from the reference through to the output. When the reference clock is delivered to the synthesizer with accumulated system noise, the solution isn’t a better synthesizer. The solution is ensuring a clean input.
A well-specified jitter attenuator IC placed ahead of the synthesizer reference input — or in the clock distribution path feeding sensitive ADCs or other downstream devices — addresses the problem at the right point. The Mixed-Signal MS1510, for example, accepts inputs up to 750 MHz and delivers regenerated outputs up to 2.2 GHz with sub-20-femtosecond phase jitter, giving downstream components a reference quality that reflects the original oscillator performance rather than the accumulated noise of the distribution path.
Building a Clocking Architecture That Holds Up
The engineers who get clocking right treat it as an architecture problem, not a component selection problem. That means asking questions at the system level first: where does jitter enter the chain, where does it get multiplied, and where can it be removed efficiently?
For a frequency synthesizer driving a phased array radar or a wideband receiver, that system-level view means characterizing the reference source, understanding the path from oscillator to synthesizer input, placing attenuation where it has the most leverage, and selecting a synthesizer whose architecture — not just whose data sheet — aligns with the application’s actual operating conditions.
Mixed-Signal Devices designs timing products from the ground up for exactly these kinds of demanding applications. Their product portfolio — spanning ultra-low-jitter oscillators, VCXOs, TCXOs, jitter attenuators, frequency multipliers, and the MS4022 high-performance frequency synthesizer covering 675 MHz to 22.6 GHz at sub-25-femtosecond jitter — gives system designers a coherent, compatible set of building blocks for the full clocking chain.
Find the Right Precision Timing Solution for Your Design
If you’re working through a clocking architecture challenge — whether it’s phase noise budget, jitter specification compliance, reference selection, or frequency synthesis to microwave frequencies — Mixed-Signal Devices has the product depth and application expertise to help.
Visit mixed-signal.com/products to explore the full product portfolio, download datasheets, and use the Phase Noise Look-Up Tool to compare performance across operating conditions. Reach out directly at info@mixed-signal.com or call (949) 679-9080 to talk through your specific design requirements.